2 nm process explained

In semiconductor manufacturing, the "2 nm process" is the next MOSFET (metal–oxide–semiconductor field-effect transistor) die shrink after the "3 nm" process node.

The term "2 nanometer" or alternatively "20 angstrom" (a term used by Intel) has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by the Institute of Electrical and Electronics Engineers (IEEE), a "2.1 nm node range label" is expected to have a contacted gate pitch of 45 nanometers and a tightest metal pitch of 20 nanometers.

Process Gate pitch Metal pitch Year
60 nm 40 nm 2018
51 nm 30 nm 2020
3 nm 48 nm 24 nm 2022
2 nm 45 nm 20 nm 2025
42 nm 16 nm 2027

As such, "2 nm" is used primarily as a marketing term by the semiconductor industry to refer to a new, improved generation of chips in terms of increased transistor density (a higher degree of miniaturization), increased speed, and reduced power consumption compared to the previous "3 nm" node generation.[1] [2]

As of May 2022, TSMC was expected to begin risk "2 nm" production at the end of 2024 and mass production in 2025;[3] Intel at that time forecasted production in 2024,[4] and Samsung in 2025.[5]

Background

By 2018, a number of transistor architectures had been proposed for the eventual replacement of FinFET, most of which were based on the concept of GAAFET:[6] horizontal and vertical nanowires, horizontal nanosheet transistors[7] [8] (Samsung MBCFET, Intel Nanoribbon), vertical FET (VFET) and other vertical transistors,[9] [10] complementary FET (CFET), stacked FET, several kinds of horizontal gate-all-around transistors such as nano-ring, hexagonal wire, square wire, and round wire gate-all-around transistors[11] and negative-capacitance FET (NC-FET) which uses drastically different materials.[12]

In late 2018, TSMC chairman Mark Liu predicted chip scaling would continue to "3 nm" and "2 nm" nodes; however, as of 2019, other semiconductor specialists were undecided as to whether nodes beyond "3 nm" could become viable. TSMC began research on "2 nm" in 2019—expecting to transition from FinFET to GAAFET transistor type. In July 2021, TSMC received governmental approval to build its "2 nm" plant. In August 2020, it began building an R&D lab for "2 nm" technology in Hsinchu, expected to become partially operational by 2021. In September 2020, TSMC confirmed this and stated that it could also install production at Taichung depending on demand. According to the Taiwan Economic Daily (2020), expectations were for high yield risk production in late 2023. According to Nikkei, the company at that time expected to have been installing production equipment for "2 nm" by 2023.[13]

Intel's 2019 roadmap scheduled potentially equivalent "3 nm" and "2 nm" nodes for 2025 and 2027, respectively, and in December 2019 announced plans for "1.4 nm" production in 2029.

At the end of 2020, seventeen European Union countries signed a joint declaration to develop their entire semiconductor industry, including developing process nodes as small as "2 nm", as well as designing and manufacturing custom processors, assigning up to €145 billion in funds.

In May 2021, IBM announced it had produced chips with "2 nm class" GAAFET transistors using three silicon layer nanosheets with a gate length of 12 nm.[14]

In July 2021, Intel unveiled its process node roadmap from 2021 onwards. The company confirmed their "2 nm" process node called "Intel 20A", with the "A" referring to angstrom (a unit equivalent to 0.1 nanometers).[15] At the same time, they introduced a new process node naming scheme that aligned their product names with similar designations from their main competitors. Intel's "20A" node was at that time projected to have been their first to move from FinFET to Gate-All-Around transistors (GAAFET); Intel's version was named 'RibbonFET'. Their 2021 roadmap scheduled the Intel "20A" node for volume production in 2024 and Intel "18A" for 2025.

In October 2021, at Samsung Foundry Forum 2021, Samsung announced it would start mass production with its MBCFET (multi-bridge channel FET, Samsung's version of GAAFET) "2 nm" process in 2025.[16]

In April 2022, TSMC announced its GAAFET "N2" process technology would enter risk production phase at the end of 2024 and production phase in 2025.[17] In July 2022, TSMC announced that its "N2" process technology was expected to feature backside power delivery and was expected to offer 10–15% higher performance at iso power or 20–30% lower power at iso performance and over 20% higher transistor density compared to N3E.[18]

In July 2022, Samsung made a number of disclosures regarding the company's previously forthcoming process technology called "2GAP" ("2nm Gate All-around Production"): the process previously remained on track for 2025 launch into mass production; number of nanosheets was projected to increase from 3 in "3GAP" to 4; the company worked on several improvements of metallization, namely "single-grain metal" for low-resistance vias and direct-etched metal interconnect planned for "2GAP" and beyond.[19]

In August 2022, a consortium of Japanese companies funded a new venture with government support called Rapidus for manufacturing of "2 nm" chips. Rapidus signed agreements with imec[20] and IBM[21] in December 2022.

In April 2023, at its Technology Symposium, TSMC introduced two more processes of its "2nm" technology platform: "N2P" featuring backside power delivery and scheduled for 2026 and "N2X" for high-performance applications. It was also revealed that ARM Cortex-A715 core fabbed on N2 process using high-performance standard library gained 16.4% of speed at iso power, saved 37.2% of power at iso speed, or gained ~10% of speed and saved ~20% of power simultaneously at iso voltage (0.8 V) compared to the core fabbed on N3E using 3-2 fin library.[22]

"2 nm" process nodes

Samsung[23] [24] [25] TSMCIntel
Process nameSF2 SF2P SF2X SF2ZN2 N2P N2X20A 18A
Transistor typeMBCFETGAAFETRibbonFET
Transistor density (MTr/mm2)
SRAM bit-cell size (μm2)
Transistor gate pitch (nm)
Interconnect pitch (nm)
Release status[26] [27]
2024 volume production

2025 H1 production[28]

Beyond 2 nm

In July 2021, Intel reported that they planned "18A" production for 2025.[15] Intel's February 2022 roadmap added that "18A" was previously expected to have delivered 10% improvement in performance per watt compared to Intel "20A". Intel's August 2024 newsroom announcement further indicated that the "18A" process should be manufacturing-ready for 2025 H1.[29]

In December 2021, Vertical-Transport FET (VTFET) CMOS logic transistor design with a vertical nanosheet was demonstrated at sub-45 nm gate pitch.[30]

In May 2022, imec presented a process technology roadmap which extends the current biannual cadence of node introduction and square-root-of-two node naming rule to 2036. The roadmap ends with process node "A2" (a metaphor for the concept of 2 angstroms), named by analogy with TSMC's naming scheme to be introduced by then.[31]

Apart from dimensional scaling of transistor structures and interconnect, innovations forecast by imec were as follows:

In September 2022, Samsung presented their future business goals, which at that time included an aim to mass-produce "1.4 nm" by 2027.[32]

As of 2023, Intel, TSMC and Samsung have all demonstrated CFET transistors. These transistors are made up of two stacked horizontal nanosheet transistors, one transistor is of the p-type (a pFET transistor) and the other transistor is of the n-type (an nFET transistor).[33]

Notes and References

  1. Web site: TSMC's 7nm, 5nm, and 3nm "are just numbers… it doesn't matter what the number is" . 10 September 2019 . 20 April 2020 . 17 June 2020 . https://web.archive.org/web/20200617230408/https://www.pcgamesn.com/amd/tsmc-7nm-5nm-and-3nm-are-just-numbers . live .
  2. A Better Way to Measure Progress in Semiconductors: It's time to throw out the old Moore's Law metric . Samuel K. Moore . IEEE . IEEE Spectrum . 21 July 2020 . 20 April 2021 . 2 December 2020 . https://web.archive.org/web/20201202002819/https://spectrum.ieee.org/semiconductors/devices/a-better-way-to-measure-progress-in-semiconductors . live .
  3. Web site: TSMC Roadmap Update: 3nm in Q1 2023, 3nm Enhanced in 2024, 2nm in 2025. 2021-10-18. AnandTech. en-us. 23 March 2022. 23 March 2022. https://web.archive.org/web/20220323103821/https://www.anandtech.com/show/17013/tsmc-update-3nm-in-q1-2023-3nm-enhanced-in-2024-2nm-in-2025. live.
  4. Web site: Intel Technology Roadmaps and Milestones. 2022-02-17. Intel. en-us. 15 March 2022. 16 July 2022. https://web.archive.org/web/20220716192641/https://www.intel.com/content/www/us/en/newsroom/news/intel-technology-roadmaps-milestones.html. live.
  5. Web site: Samsung Foundry: 2nm Silicon in 2025. 2021-10-06. AnandTech. en-us. 23 March 2022. 23 March 2022. https://web.archive.org/web/20220323114436/https://www.anandtech.com/show/16995/samsung-foundry-2nm-silicon-in-2025. live.
  6. Web site: The Increasingly Uneven Race to 3nm/2nm . 24 May 2021 .
  7. Web site: What's Different About Next-Gen Transistors . 20 October 2022 .
  8. Web site: Intel's Stacked Nanosheet Transistors Could be the Next Step in Moore's Law .
  9. Web site: Nanowire Transistors Could Keep Moore's Law Alive .
  10. Web site: Nanowires give vertical transistors a boost . 2 August 2012 .
  11. Web site: What's After FinFETs? . 24 July 2017 .
  12. Web site: Transistor Options Beyond 3nm . 15 February 2018 .
  13. Web site: Taiwan gives TSMC green light for most advanced chip plant. 2021-08-24. Nikkei Asia. en-GB. 4 November 2021. https://web.archive.org/web/20211104002128/https://asia.nikkei.com/Business/Tech/Semiconductors/Taiwan-gives-TSMC-green-light-for-most-advanced-chip-plant. live.
  14. 12 nm gate length is the dimension defined by the IRDS 2020 to be associated with the "1.5 nm" process node: https://irds.ieee.org/images/files/pdf/2020/2020IRDS_MM.pdf
  15. Web site: Cutress. Dr Ian. Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!. 2021-07-27. 26 July 2021. www.anandtech.com. 3 November 2021. https://web.archive.org/web/20211103110548/https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros. live.
  16. Web site: Samsung Foundry Innovations Power the Future of Big Data, AI/ML and Smart, Connected Devices. Samsung. 2021-10-07. 9 May 2022. 8 April 2022. https://web.archive.org/web/20220408182045/https://news.samsung.com/global/samsung-foundry-innovations-power-the-future-of-big-data-ai-ml-and-smart-connected-devices. live.
  17. Web site: TSMC roadmap update: N3E in 2024, N2 in 2026, major changes incoming. AnandTech. 2022-04-22. 9 May 2022. 9 May 2022. https://web.archive.org/web/20220509122111/https://www.anandtech.com/print/17356/tsmc-roadmap-update-n3e-in-2024-n2-in-2026-major-changes-incoming. live.
  18. Web site: TSMC Q2 2022 Earnings Call. TSMC. 2022-07-14. 22 July 2022. 15 July 2022. https://web.archive.org/web/20220715105421/https://investor.tsmc.com/english/encrypt/files/encrypt_file/reports/2022-07/185efaefea866a5e944499cda9eeecc65315449c/TSMC%202Q22%20Transcript.pdf. live.
  19. Web site: Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements . WikiChip Fuse . 2022-07-05.
  20. Web site: Manners . David . 2022-12-16 . Imec and Rapidus sign up for 2nm . Electronics Weekly . en.
  21. Web site: Japan to Manufacture 2nm Chips With a Little Help From IBM . 2022-12-13 . Matthew . Humphries . PCMAG . en.
  22. Web site: TSMC Outlines 2nm Plans: N2P Brings Backside Power Delivery in 2026, N2X Added To The Roadmap. AnandTech. 2023-04-26.
  23. Web site: Samsung Foundry: 2nm Silicon in 2025 . AnandTech . 2021-10-06.
  24. https://www.anandtech.com/show/21377/samsung-foundry-update-2nm-unveil-in-june-2nd-gen-3nm-hits-production-this-year
  25. https://www.anandtech.com/show/21444/samsung-foundry-unveils-updated-roadmap-2nm-evolution-through-2027
  26. https://www.anandtech.com/show/21370/tsmc-2nm-update-n2-in-2025-n2p-loses-bspdn-nanoflex-optimizations
  27. Web site: Intel Unveils Meteor Lake Architecture: Intel 4 Heralds the Disaggregated Future of Mobile CPUs .
  28. https://www.techpowerup.com/321900/intel-reports-first-quarter-2024-financial-results
  29. Web site: Intel 18A powered on and healthy, on track for next-gen client and server chip production next year. Intel. 2024-08-06.
  30. Book: https://ieeexplore.ieee.org/document/9720561 . 10.1109/IEDM19574.2021.9720561 . 247321213 . Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices . 2021 IEEE International Electron Devices Meeting (IEDM) . 2021 . Jagannathan . H. . Anderson . B. . Sohn . C-W. . Tsutsui . G. . Strane . J. . Xie . R. . Fan . S. . Kim . K-I. . Song . S. . Sieg . S. . Seshadri . I. . Mochizuki . S. . Wang . J. . Rahman . A. . Cheon . K-Y. . Hwang . I. . Demarest . J. . Do . J. . Fullam . J. . Jo . G. . Hong . B. . Jung . Y. . Kim . M. . Kim . S. . Lallement . R. . Levin . T. . Li . J. . Miller . E. . Montanini . P. . Pujari . R. . 26.1.1–26.1.4 . 978-1-6654-2572-8 . 1 .
  31. Web site: Imec Presents Sub-1nm Process and Transistor Roadmap Until 2036. Tom's Hardware. 2022-05-21.
  32. Web site: Samsung Electronics Unveils Plans for 1.4nm Process Technology and Investment for Production Capacity at Samsung Foundry Forum 2022. Samsung Global Newsroom. 2022-10-04.
  33. Web site: Intel, Samsung, and TSMC Demo 3D-Stacked Transistors - IEEE Spectrum .